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? 1997 integrated device technology, inc. 1 integrated device technology, inc. commercial/industrial temperature range idt79r4640 idt79rv4640 block diagram features high-performance embedded 64-bit microprocessor - 64-bit integer operations - 64-bit registers - based on the mips risc architecture - 80mhz, 100mhz, 133 mhz and 150mhz operation frequency - 32-bit bus interface brings 64-bit power to 32-bit sys- tem cost high-performance dsp capability - 75 million integer mul-accumulate operations/sec @150mhz - 50 mflops ?ating-point operations @150mhz high-performance microprocessor - 75 m mul-add/second @150mhz - 50 mflops @150mhz - >340,000 dhrystone (2.1)/sec capability @133mhz (197 dhrystone mips) high level of integration - 64-bit, 150 mhz integer cpu - 50mflops single-precision ?ating-point unit - 8kb instruction cache; 8kb data cache - integer multiply unit with 75m mul-add/sec upwardly software compatible with idt riscontroller family easily upgradable to 64-bit system low-power operation - active power management powers-down inactive units - standby mode large, ef?ient on-chip caches - separate 8kb instruction and 8kb data caches - over 1800mb/sec bandwidth from internal caches - 2-set associative - write-back and write-through support - cache locking to facilitate deterministic response - high performance write protocols for graphics and data communications bus compatible with orion family - system interfaces to 67 mhz, provides bandwidth up to 266 mb/sec - direct interface to 32-bit wide systems - synchronized to external reference clock for multi- master operation improved real-time support - fast interrupt decode - optional cache locking 150 mhz 64-bit orion cpu 64-bit register file 64-bit adder store aligner logic unit load aligner high-performance integer multiply pipeline control fp register file fp add/sub/cvt/ pack/unpack fp multiply pipeline control 50mflops single-precision fpa div/sqrt 32-bit synchronized system interface address translation/ cache attribute control exception management functions system control coprocessor data cache data cache instruction bus control bus data bus set a (lockable) set b instruction cache set b instruction cache set a (lockable) low-cost embedded orion risc microprocessor may 1997 the idt logo is a registered trademark and orion, r4650, r4640, rv4640, r4600, r3081, r3052, r3051, r3041, r5000, r36100 , riscontroller, and riscore 3486/1 integrated device technology, inc. are trademarks of
r4640/rv4640 commercial/industrial temperature range 2 description the idt79r4640 is a low-cost member of the integrated device technology, inc. orion family, targeted to a variety of performance-hungry embedded applica- tions. the r4640 continues the orion tradition of high- performance through high-speed pipelines, high-band- width caches and bus interface, 64-bit architecture, and careful attention to ef?ient control. the cost of this performance is reduced by removing functional units frequently not required for many embedded applications. the r4640 supports a wide variety of embedded processor-based applications, such as internetworking equipment (routers, switches), of?e automation equip- ment (printers, scanners), and consumer multimedia game systems. also, being upwardly software-compatible with the riscontroller family as well as bus- and upwardly software-compatible with the idt orion family, the r4640 will serve in many of the same applications. and, the r4640 supports applications that require integer digital signal processing (dsp) functions. the r4640 brings orion performance levels to lower cost systems. orion performance is preserved by retaining large on-chip two-way set-associative caches, a streamlined high-speed pipeline, high bandwidth, 64-bit execution, and facilities such as early restart for data cache misses. these techniques allow the system designer over 1.8 gb/sec aggregate internal bandwidth, 266 mb/sec bus bandwidth, almost 200 dhrystone mips, 50mflops, and 75 m mul-add/sec. an array of tools facilitates rapid development of r4640-based systems, allowing a wide variety of customers access to the processors high- performance capabilities while maintaining short time-to- market goals. hardware overview some key elements of the r4640 are brie? described below. more detailed information is available in the idt79r4640/idt79r4650 risc processor hard- ware users manual . pipeline the r4640 uses a 5-stage pipeline that is similar to the idt79r3000 and the idt79r4700 processors. the simplicity of this pipeline allows the r4640 to cost less than super-scalar processors and require less power than super-pipelined processors. so, unlike superscalar processors, applications that have large data dependen- cies or require a great deal of load/stores can still achieve peak performance. integer execution engine the r4640 implements the mips-iii instruction set architecture, and thus is fully upward compatible with applications running on the earlier generation parts. the r4640 is software-compatible with the r4650, and includes the instruction set found in the r4700 micropro- cessor, targeted at higher performance while maintaining binary compatibility with earlier r30xx processors. the extensions result in better code density, greater multi- processing support, improved performance for commonly used code sequences in operating system kernels, and faster execution of floating-point intensive applications. all resource dependencies are made transparent to the programmer, insuring transportability among implementa- tions of the mips instruction set architecture. in addition, mips-iii specifies new instructions defined to take advantage of the 64-bit architecture of the processor. finally, the r4640 also implements additional instruc- tions, which are considered extensions to the mips-iii architecture. these instructions improve the multiply and multiply-add throughput of the cpu, making it well suited to a wide variety of imaging and dsp applications. these extensions, which use opcodes allocated by mips technologies for this purpose, are supported by a wide variety of development tools. the mips integer unit implements a load/store archi- tecture with single cycle alu operations (logical, shift, add, sub) and autonomous multiply/divide unit. the 64-bit register resources include: 32 general-purpose orthogonal integer registers, the hi/lo result registers for the integer multiply/divide unit, and the program counter. in addition, the on-chip floating-point co-processor adds 32 floating-point registers, and a floating-point control/status register. register file the r4640 has 32 general-purpose 64-bit registers. these registers are used for scalar integer operations and address calculation. the register ?e consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. arithmetic logic unit the r4640 alu consists of the integer adder and logic unit. the adder performs address calculations in addition to arithmetic operations; the logic unit performs all of the logic and shift operations. each unit is highly optimized and can perform an operation in a single pipe- line cycle. integer multiply/divide the r4640 uses a dedicated integer multiply/divide unit, optimized for high-speed multiply and multiply- accumulate operation. table 1 shows the performance, expressed in terms of pipeline clocks, achieved by the r4640 integer multiply unit.
r4640/rv4640 commercial/industrial temperature range 3 the mips-iii architecture defines that the results of a multiply or divide operation are placed in the hi and lo registers. the values can then be transferred to the general purpose register file using the mfhi/mflo instructions. the r4640 adds a new multiply instruction, ?ul? which can specify that the multiply results bypass the ?o register and are placed immediately in the primary register file. by avoiding the explicit ?ove-from-lo instruction required when using ?o? throughput of multiply-intensive operations is increased. an additional enhancement offered by the r4640 is an atomic ?ultiply-add?operation, mad, used to perform multiply-accumulate operations. this instruction multiplies two numbers and adds the product to the current contents of the hi and lo registers. this operation is used in numerous dsp algorithms, and allows the r4640 to cost reduce systems requiring a mix of dsp and control functions. finally, aggressive implementation techniques feature low latency for these operations along with pipelining to allow new operations to be issued before a previous one has fully completed. table 1 also shows the repeat rate (peak issue rate), latency, and number of processor stalls required for the various operations. the r4640 performs automatic operand size detection to determine the size of the operand, and implements hardware interlocks to prevent overrun, allowing this high-performance to be achieved with simple programming. floating-point coprocessor the r4640 incorporates an entire single-precision ?ating-point coprocessor on chip, including a ?ating- point register ?e and execution units. the ?ating-point coprocessor forms a ?eamless interface with the integer unit, decoding and executing instructions in parallel with the integer unit. opcode operand size latency repeat stall mult/u, mad/u 16 bit 3 2 0 32 bit 4 3 0 mul 16 bit 3 2 1 32 bit 4 3 2 dmult, dmultu any 6 5 0 div, divu any 36 36 0 ddiv, ddivu any 68 68 0 table 1: r4640 integer multiply operation the oating-point unit of the r4640 directly imple- ments single-precision oating-point operations, which enables the r4640 to perform functions such as graphics rendering without requiring extensive die area or power consumption. the single-precision unit of the r4640 is directly compatible with the single-precision operation of the r4700, and features the same latencies and repeat rates. the r4640 does not directly implement the double- precision operations found in the r4700. however, to maintain software compatibility, the r4640 will signal a trap when a double-precision operation is initiated, allowing the requested function to be emulated in software. alternatively, the system architect could use a software library emulation of double-precision functions, selected at compile time, to eliminate the overhead associated with trap and emulation. floating-point units the r4640s ?ating-point execution units perform single precision arithmetic, as speci?d in ieee standard 754. the execution unit is broken into a separate multiply unit and a combined add/convert/divide/square root unit. overlap of multiply and add/subtract is supported. the multiplier is partially pipelined, allowing a new multiplica- tion instruction to begin every 6 cycles. as in the idt79r4700, the r4640 maintains fully precise floating-point exceptions while allowing both overlapped and pipelined operations. precise exceptions are extremely important in mission-critical environments, such as ada, and highly desirable for debugging in any environment. the floating-point unit? operation set includes floating- point add, subtract, multiply, divide, square root, conversion between fixed-point and floating-point format, conversion among floating-point formats, and floating- point compare. these operations comply with ieee standard 754. double precision operations are not directly supported; attempts to execute double-precision floating point operations, or refer directly to double- precision registers, result in the r4640 signalling a ?rap to the cpu, enabling emulation of the requested function.
r4640/rv4640 commercial/industrial temperature range 4 table 2 gives the latencies of some of the floating-point instructions in internal processor cycles. floating-point general register file the ?ating-point register ?e is made up of thirty-two 32-bit registers. these registers are used as source or target registers for the single-precision operations. references to these registers as 64-bit registers (as supported in the r4700) will cause a trap to be signalled to the integer unit. the floating-point control register space contains two registers; one for determining configuration and revision information for the coprocessor and one for control and status information. these are primarily involved with diagnostic software, exception handling, state saving and restoring, and control of rounding modes. system control coprocessor (cp0) the system control coprocessor in the mips archi- tecture is responsible for the virtual to physical address translation and cache protocols, the exception control system, and the diagnostics capability of the processor. in the mips architecture, the system control coprocessor (and thus the kernel software) is implementation dependent. in the r4640, significant changes in cp0 relative to the r4600 have been implemented. these changes are designed to simplify memory management, facilitate debug, and speed real-time processing. operation instruction latency add 4 sub 4 mul 8 div 32 sqrt 31 cmp 3 fix 4 float 6 abs 1 mov 1 neg 1 lwc1 2 swc1 1 table 2: floating-point operation system control coprocessor registers the r4640 incorporates all system control co- processor (cp0) registers on-chip. these registers provide the path through which the virtual memory system? address translation is controlled, exceptions are handled, and operating modes are controlled (kernel vs. user mode, interrupts enabled or disabled, cache features). in addition, the r4640 includes registers to implement a real-time cycle counting facility, which aids in cache diagnostic testing, assists in data error detection, and facilitates software debug. alternatively, this timer can be used as the operating system reference timer, and can signal a periodic interrupt. table 3 shows the cp0 registers of the r4640. operation modes the r4640 supports two modes of operation: user mode and kernel mode. kernel mode operation is typically used for exception handling and operating system kernel functions, including number name function 0 ibase instruction address space base (new in r4640) 1 ibound instruction address space bound (new in r4640) 2 dbase data address space base (new in r4640) 3 dbound data address space bound (new in r4640) 4-7, 10, 20-25, 29, 31 - not used 8 badvaddr virtual address on address exceptions 9 count counts every other cycle 11 compare generate interrupt when count = compare 12 status miscellaneous control/status 13 cause exception/interrupt information 14 epc exception pc 15 prid processor id 16 con? cache and system attributes 17 calg cache attributes for the 8 512mb regions of the virtual address space 18 iwatch instruction breakpoint virtual address 19 dwatch data breakpoint virtual address 26 ecc used in cache diagnostics 27 cacheerr cache diagnostic information 28 taglo cache index information 30 errorepc cacheerror exception pc table 3: r4640 cpo registers
r4640/rv4640 commercial/industrial temperature range 5 cp0 management and access to io devices. in kernel mode, software has access to the entire address space and all of the co-processor 0 registers, and can select whether to enable co-processor 1 accesses. the processor enters kernel mode at reset, and whenever an exception is recognized. user mode is typically used for applications programs. user mode accesses are limited to a subset of the virtual address space, and can be inhibited from accessing cp0 functions. virtual-to-physical address mapping the 4gb virtual address space of the r4640 is shown in figure 3. the 4 gb address space is divided into addresses accessible in either kernel or user mode (kuseg), and addresses only accessible in kernel mode (kseg2:0). the r4640 supports the use of multiple user tasks sharing common virtual addresses, but mapped to separate physical addresses. this facility is implemented via the ?ase-bounds?registers contained in cp0. when a user virtual address is asserted (load, store, or instruction fetch), the r4640 compares the virtual address with the contents of the appropriate ?ounds?register (instruction or data). if the virtual address is ?n bounds? the value of the corresponding ?ase?register is added to 0xffffffff 0xc0000000 kernel virtual address space (kseg2) unmapped, 1.0 gb 0xbfffffff 0xa0000000 uncached kernel physical address space (kseg1) unmapped, 0.5gb 0x9fffffff 0x80000000 cached kernel physical address space (kseg0) unmapped, 0.5gb 0x7ffffff 0x00000000 user virtual address space (useg) mapped, 2.0gb figure 3: mode virtual addressing (32-bit mode) the virtual address to form the physical address for that reference. if the address is not within bounds, an exception is signalled. this facility enables multiple user processes in a single physical memory without the use of a tlb. this type of operation is further supported by a number of devel- opment tools for the r4640, including real-time operating systems and ?osition independent code? kernel mode addresses do not use the base-bounds registers, but rather undergo a fixed virtual to physical address translation. debug support to facilitate software debug, the r4640 adds a pair of ?atch?registers to cp0. when enabled, these registers will cause the cpu to take an exception when a ?atched?address is appropriately accessed. interrupt vector the r4640 also adds the capability to speed interrupt exception decoding. unlike the r4700, which utilizes a single common exception vector for all exception types (including interrupts), the r4640 allows kernel software to enable a separate interrupt exception vector. when enabled, this vector location speeds interrupt processing by allowing software to avoid decoding interrupts from general purpose exceptions. cache memory to keep the r4640? high-performance pipeline full and operating efficiently, the r4640 incorporates on-chip instruction and data caches that can each be accessed in a single processor cycle. each cache has its own 64-bit data path and can be accessed in parallel. the cache subsystem provides the integer and floating-point units with an aggregate bandwidth of over 1800 mb per second at a pipeline clock frequency of 150mhz. the cache subsystem is similar in construction to that found in the r4600, although some changes have been implemented. table 6 is an overview of the caches found on the r4640. instruction cache the r4640 incorporates a two-way set associative on- chip instruction cache. this virtually indexed, physically tagged cache is 8kb in size and is parity protected. because the cache is virtually indexed, the virtual-to- physical address translation occurs in parallel with the cache access, thus further increasing performance by allowing these two operations to occur simultaneously. the tag holds a 20-bit physical address and valid bit, and is parity protected. the instruction cache is 64-bits wide, and can be refilled or accessed in a single processor cycle. instruction fetches require only 32 bits per cycle, for a peak instruction bandwidth of 600mb/sec at 150mhz. sequential accesses take advantage of the 64-bit fetch to reduce power dissipation, and cache miss refill, can write
r4640/rv4640 commercial/industrial temperature range 6 64 bits-per-cycle to minimize the cache miss penalty. the line size is eight instructions (32 bytes) to maximize performance. in addition, the contents of one set of the instruction cache (set ?? can be ?ocked?by setting a bit in a cp0 register. locking the set prevents its contents from being overwritten by a subsequent cache miss; refill occurs then only into ?et b? this operation effectively ?ocks?time critical code into one 4kb set, while allowing the other set to service other instruction streams in a normal fashion. thus, the benefits of cached performance are achieved, while deterministic real-time response is preserved. data cache for fast, single cycle data access, the r4640 includes an 8kb on-chip data cache that is two-way set associative with a fixed 32-byte (eight words) line size. table 4 lists the r4640 cache attributes. the data cache is protected with byte parity and its tag is protected with a single parity bit. it is virtually indexed and physically tagged to allow simultaneous address translation and data cache access the normal write policy is writeback, which means that a store to a cache line does not immediately cause memory to be updated. this increases system perfor- mance by reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish before issuing a subsequent memory operation. software can however select write-through for certain address ranges, using the calg register in cp0. cache protocols supported for the data cache are: uncached . addresses in a memory area indicated as uncached will not be read from the cache. stores to such addresses will be written directly to main memory, characteristics instruction data size 8kb 8kb organization 2-way set associa- tive 2-way set associa- tive line size 32b 32b index vaddr 11..0 vaddr 11..0 ta g paddr 31..12 paddr 31..12 write policy n.a. writeback /writethru line transfer order read sub-block order read sub-block order write sequential write sequential miss restart after transfer of entire line ?st word parity per-word per-byte cache locking set a set a table 4: r4640 cache attributes without changing cache contents. writeback . loads and instruction fetches will ?st search the cache, reading main memory only if the desired data is not cache resident. on data store opera- tions, the cache is ?st searched to see if the target address is cache resident. if it is resident, the cache contents will be updated, and the cache line marked for later writeback. if the cache lookup misses, the target line is ?st brought into the cache before the cache is updated. write-through with write allocate. loads and instruc- tion fetches will ?st search the cache, reading main memory only if the desired data is not cache resident. on data store operations, the cache is ?st searched to see if the target address is cache resident. if it is resi- dent, the cache contents will be updated and main memory will also be written; the state of the ?riteback bit of the cache line will be unchanged. if the cache lookup misses, the target line is ?st brought into the cache before the cache is updated. write-through without write-allocate. loads and instruction fetches will ?st search the cache, reading main memory only if the desired data is not cache resi- dent. on data store operations, the cache is ?st searched to see if the target address is cache resident. if it is resident, the cache contents will be updated, and the cache line marked for later writeback. if the cache lookup misses, then only main memory is written. associated with the data cache is the store buffer. when the r4640 executes a store instruction, this single- entry buffer gets written with the store data while the tag comparison is performed. if the tag matches, then the data is written into the data cache in the next cycle that the data cache is not accessed (the next non-load cycle). the store buffer allows the r4640 to execute a store every processor cycle and to perform back-to-back stores without penalty. write buffer writes to external memory, whether cache miss write- backs or stores to uncached or write-through addresses, use the on-chip write buffer. the write buffer holds up to four address and data pairs. the entire buffer is used for a data cache writeback and allows the processor to proceed in parallel with memory update. for uncached and write-through stores, the write buffer significantly increases performance over the r4000 family of processors. system interface the r4640 supports a 64-bit system interface that is bus compatible with the r4700 system interface. in addition, the r4640 supports a 32-bit system interface mode, allowing the cpu to interface directly with a lower cost memory system.
r4640/rv4640 commercial/industrial temperature range 7 the interface consists of a 64-bit address/data bus with 8 check bits and a 9-bit command bus protected with parity. in addition, there are 8 handshake signals and 6 interrupt inputs. the interface has a simple timing specifi- cation and is capable of transferring data between the processor and memory at a peak rate of 533mb/sec at 133mhz. figure 4 shows a typical system using the r4640. in this example two banks of drams are used to supply and accept data with a ddxxdd data pattern. the r4640 clocking interface allows the cpu to be easily mated with external reference clocks. the cpu input clock is the bus reference clock, and can be between 25 and 67mhz (somewhat dependent on maximum pipeline speed for the cpu). an on-chip phase-locked-loop generates the pipeline clock from the system interface clock by multiplying it up an amount selected at system reset. supported multi- pliers are values 2 through 8 inclusive, allowing systems to implement pipeline clocks at significantly higher frequency than the system interface clock. system address/data bus the 64-bit system address data (sysad) bus is used to transfer addresses and data between the r4640 and the rest of the system. it is protected with an 8-bit parity check bus, sysadc. when initialized for 32-bit operation, sysad can be viewed as a 32-bit multiplexed bus, with 4 parity check bits. the system interface is configurable to allow easier interfacing to memory and i/o systems of varying frequencies. the bus frequency and reference timing of the r4640 are taken from the input clock. the rate at which the cpu transmits data to the system interface is programmable via boot time mode control bits. the rate at which the processor receives data is fully controlled by the external device. therefore, either a low cost interface requiring no read or write buffering or a faster, high perfor- mance interface can be designed to communicate with the r4640. again, the system designer has the flexibility to make these price/performance trade-offs. system command bus the r4640 interface has a 9-bit system command (syscmd) bus. the command bus indicates whether the sysad bus carries an address or data. if the sysad carries an address, then the syscmd bus also indicates what type of transaction is to take place (for example, a read or write). if the sysad carries data, then the syscmd bus also gives information about the data (for example, this is the last data word transmitted, or the cache state of this data line is clean exclusive). the syscmd bus is bidirectional to support both processor requests and external requests to the r4640. processor requests are initiated by the r4640 and responded to by an external device. external requests are issued by an external device and require the r4640 to respond. the r4640 supports single datum (one to eight byte) and 8-word block transfers on the sysad bus. in the case of a single-datum transfer, the low-order 3 address bits gives the byte address of the transfer, and the syscmd bus indicates the number of bytes being transferred. the choice of 32- or 64-bit wide system interface dictates whether a cache line block transaction requires 4 double rv4640 memory i/o controller control address scsi enet 32 9 boot rom dram (80ns) 2 11 figure 4: typical r4640 system architecture
r4640/rv4640 commercial/industrial temperature range 8 word data cycles or 8 single word cycles, and whether a single data transfer larger than 4 bytes should be broken into two smaller transfers. handshake signals there are six handshake signals on the system interface. two of these, rdrdy* and wrrdy* are used by an external device to indicate to the r4640 whether it can accept a new read or write transaction. the r4640 samples these signals before deasserting the address on read and write requests. extrqst* and release* are used to transfer control of the sysad and syscmd buses between the processor and an external device. when an external device needs to control the interface, it asserts extrqst*. the r4640 responds by asserting release* to release the system interface to slave state. validout* and validin* are used by the r4640 and the external device respectively to indicate that there is a valid command or data on the sysad and syscmd buses. the r4640 asserts validout* when it is driving these buses with a valid command or data, and the external device drives validin* when it has control of the buses and is driving a valid command or data. non-overlapping system interface the r4640 requires a non-overlapping system interface, compatible with the r4700. this means that only one processor request may be outstanding at a time and that the request must be serviced by an external device before the r4640 issues another request. the r4640 can issue read and write requests to an external device, and an external device can issue read and write requests to the r4640. the r4640 asserts validout* and simultaneously drives the address and read command on the sysad and syscmd buses. if the system interface has rdrdy* or read transactions asserted, then the processor tristates its drivers and releases the system interface to slave state by asserting release*. the external device can then begin sending the data to the r4640. figure 5 shows a processor block read request and the external agent read response. the read latency is 4 cycles (validout* to validin*), and the response data pattern is ddxxdd. figure 6 shows a processor block write. write reissue and pipeline write the r4700 and the r4640 implement additional write protocols designed to improve performance. this imple- mentation doubles the effective write bandwidth. the write re-issue has a high repeat rate of 2 cycles per write. a write issues if wrrdy is asserted 2 cycles earlier and is still asserted at the issue cycle. if it is not still asserted, the last write re-issues again. pipelined writes have the same 2-cycle per write repeat rate, but can issue one more write after wrrdy* de-asserts. they still follow the issue rule as r4x00 mode for other writes. external requests the r4640 responds to requests issued by an external device. the requests can take several forms. an external device may need to supply data in response to an r4640 read request or it may need to gain control over the system interface bus to access other resources which may be on that bus. the following is a list of the supported external requests: read response null boot-time options fundamental operational modes for the processor are initialized by the boot-time mode control interface. the boot-time mode control interface is a serial interface operating at a very low frequency (masterclock divided by 256). the low-frequency operation allows the initialization information to be kept in a low-cost eprom; alternatively the twenty-or-so bits could be generated by the system interface asic or a simple pal. immediately after the v ccok signal is asserted, the processor reads a serial bit stream of 256 bits to initialize all fundamental operational modes. after initialization is complete, the processor continues to drive the serial clock output, but no further initialization bits are read. boot-time modes the boot-time serial mode stream is de?ed in table 5. bit 0 is the bit presented to the processor when v ccok is asserted; bit 255 is the last. power management cp0 is also used to control the power management for the r4640. this is the standby mode and it can be used to reduce the power consumption of the internal core of the cpu. the standby mode is entered by executing the wait instruction with the sysad bus idle and is exited by any interrupt. standby mode operation the r4640 provides a means to reduce the amount of power consumed by the internal core when the cpu would otherwise not be performing any useful operations. this is known as ?tandby mode? entering standby mode executing the wait instruction enables interrupts and enters standby mode. when the wait instruction finishes the w pipe-stage, if the sysad bus is currently idle, the internal clocks will shut down, thus freezing the pipeline. the pll, internal timer, and some of the input pins (int[5:0]*, nmi*, extreq*, reset*, and coldreset*) will continue to run. if the conditions are not correct when the
r4640/rv4640 commercial/industrial temperature range 9 figure 5: r4640 block read request figure 6: r4640 block write request masterclock sysad addr data0 data1 data6 data7 syscmd read cdata cdata cdata ceod validout validin rdrdy wrrdy release masterclock sysad addr data0 data1 data6 data7 syscmd validout validin rdrdy wrrdy release write cdata cdata cdata ceod
r4640/rv4640 commercial/industrial temperature range 10 wait instruction finishes the w pipe-stage (i.e. the sysad bus is not idle), the wait is treated as a nop. once the cpu is in standby mode, any interrupt, including the internally generated timer interrupt, will cause the cpu to exit standby mode. mode bit description 0 reserved (must be zero) 4s:1 writeback data rate: 32-bit 0 ? w 1 ? wwx 2 ? wwxx 3 ? wxwx 4 ? wwxxx 5 ? wwxxxx 6 ? wxxwxx 7 ? wwxxxxxx 8 ? wxxxwxxx 9-15 reserved 7:5 clock multiplier: 0 ? 2 1 ? 3 2 ? 4 3 ? 5 4 ? 6 5 ? 7 6 ? 8 7 reserved 80 ? little endian 1 ? big endian 10:9 00 ? r4000 compatible 01 ? reserved 10 ? pipelined writes 11 ? write re-issue 11 disable the timer interrupt on int[5] 12 must be 1 14:13 output driver strength: 10 ? 100% strength (fastest) 11 ? 83% strength 00 ? 67% strength 01 ? 50% strength (slowest) 255:15 must be zero table 5: boot-time mode stream thermal considerations the r4640 utilizes special packaging techniques to improve the thermal properties of high-speed processors. the rv4640 is packaged using cavity-up packaging in a 128-pin thermally enhanced pqfp package (?u? with a drop-in heat spreader, for devices with low peak power. the r4640 also utilizes the mquad package for higher power consumption devices (the ?u package), which is an all-aluminum package with the die attached to a normal copper lead frame mounted to the aluminum casing. due to the heat-spreading effect of the aluminum, the mquad package allows for an ef?ient thermal transfer between the die and the case. the aluminum offers less internal resistance from one end of the package to the other, reducing the temperature gradient across the package and therefore presenting a greater area for convection and conduction to the pcb for a given temper- ature. even nominal amounts of air ?w will dramatically reduce the junction temperature of the die, resulting in cooler operation. the mquad package is pin and socket compatible with the 128-pin pqfp package. the r4640 is guaranteed in a case temperature range of 0 to +85 c. the type of package, speed (power) of the device, and air ?w conditions affect the equivalent ambient temperature conditions that will meet this speci?ation. the equivalent allowable ambient temperature, t a , can be calculated using the thermal resistance from case to ambient ( ? ca ) of the given package. the following equation relates ambient and case temperatures: t a = t c - p * ? ca where p is the maximum power consumption at hot temperature, calculated by using the maximum i cc speci- ?ation for the device. typical values for ? ca at various air ?ws are shown in table 6. note that the r4640 implements advanced power management to substantially reduce the average power dissipation of the device. this operation is described in the idt79r4640/ idt79r4650 risc processor hardware users manual . ? ca air?w (ft/min) 0 200 400 600 800 1000 128 pqfp (du) 21 13 10 9 8 7 128 mquad (mu) 21 13 10 9 8 7 table 6: thermal resistance ( ? ca) at various air?ws
r4640/rv4640 commercial/industrial temperature range 11 data sheet revision history changes to version dated december 1995: features: - added 32-bit bus interface info - deleted items from low-power operation descriptions. hardware overview: - added detailed descriptions of features. - changed boot time mode stream table values for mode bit 12. dc electrical characteristics: - the c in and c out values have been changed. ac electrical characteristics: - in system interface parameters tables (r4640 and rv4640), data setup and data hold minimums changed. valid combinations: - list of valid combinations has been corrected. changes to version dated march 1997: features: - added preliminary 150 mhz operation frequency thermal considerations: - added thermally enhanced packaging (?u? and drop-in heat spreader information. - upgraded 80 to 133mhz speed grade specs to ?inal.?
r4640/rv4640 commercial temperature range 12 pin description the following is a list of interface, interrupt, and miscellaneous pins available on the r4640. pin names ending with an asterisk (*) identify pins that are active when low. pin name type description system bus interface extrqst* input external request signals that the system interface needs to submit an external request. release* output release interface signals that the processor is releasing the system interface to slave state rdrdy* input read ready signals that an external agent can now accept a processor read. wrrdy* input write ready signals that an external agent can now accept a processor write request. validin* input valid input signals that an external agent is now driving a valid address or data on the sysad bus and a valid command or data identi?r on the syscmd bus. validout* output valid output signals that the processor is now driving a valid address or data on the sysad bus and a valid command or data identi?r on the syscmd bus. sysad(31:0) input/output system address/data bus a 32-bit address and data bus for communication between the processor and an exter- nal agent. sysadc(3:0) input/output system address/data check bus a 4-bit bus containing parity check bits for the sysad bus during data bus cycles. syscmd(8:0) input/output system command/data identi?r bus a 9-bit bus for command and data identi?r transmission between the processor and an external agent. syscmdp input/output reserved system command/data identi?r bus parity for the r4640 this signal is unused on input and zero on output. clock/control interface masterclock input master clock master clock input used as the system interface reference clock. all output timings are relative to this input clock. pipeline operation frequency is derived by multiplying this clock up by the factor selected during boot initialization. v cc p input quiet v cc for pll quiet v cc for the internal phase locked loop. v ss p input quiet v ss for pll quiet v ss for the internal phase locked loop.
r4640/rv4640 commercial/industrial temperature range 13 pin name type description interrupt interface int*(5:0) input interrupt six general processor interrupts, bit-wise or d with bits 5:0 of the interrupt register. nmi* input non-maskable interrupt non-maskable interrupt, ord with bit 6 of the interrupt register. initialization interface v cco k input v cc is ok when asserted, this signal indicates to the r4640 that the power supply has been above vcc minimum for more than 100 milliseconds and will remain stable. the asser- tion of v cco k initiates the reading of the boot-time mode control serial stream. coldreset* input cold reset this signal must be asserted for a power on reset or a cold reset. coldreset must be de-asserted synchronously with masterclock. reset* input reset this signal must be asserted for any reset sequence. it may be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. reset must be de-asserted synchronously with masterclock. modeclock output boot mode clock serial boot-mode data clock output at the system clock frequency divided by 256. modein input boot mode data in serial boot-mode data input.
r4640/rv4640 commercial temperature range 14 absolute maximum ratings (1) notes to absolute maximum rating table: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v in minimum = ?.0v for pulse width less than 15ns. v in should not exceed v cc +0.5 volts. 3. when v in < 0v or v in > v cc 4. not more than one output should be shorted at a time. duration of the short should not exceed 30 seconds. recommended operation temperature and supply voltage symbol rating r4640 5.0v 5% rv4640 3.3v 5% rv4640 3.3v 5% unit commercial commercial industrial v term terminal voltage with respect to gnd ?.5 (2) to +7.0 ?.5 (2) to +4.6 ?.5 (2) to +4.6 v t c operating temperature(case) 0 to +85 0 to +85 -40 to +85 c t bias case temperature under bias ?5 to +125 ?5 to +125 ?5 to +125 c t stg storage temperature ?5 to +125 ?5 to +125 ?5 to +125 c i in dc input current 20 (3) 20 (3) 20 (3) ma i out dc output current 50 (4) 50 (4) 50 (4) ma grade temperature gnd r4640 rv4640 v cc v cc commercial 0 c to +85 c (case) 0v 5.0v 5% 3.3v 5% industrial -40 + 85 c (case) 0v n/a 3.3v 5%
r4640/rv4640 commercial/industrial temperature range 15 ac electrical characteristics ?commercial temperature range?4640 (v cc =5.0v 5%; t case = 0 c to +85 c) clock parameters?4640 (2) notes to r4640/rv4640 ac/dc electrical characteristic tables: 5. guaranteed by design. 6. operation of the r4640/rv4640 is only guaranteed with the phase lock loop enabled. 7. timings are measured from 1.5v of the clock to 1.5v of the signal. 8. capacitive load for all output timings is 50pf. 9. typical integer instruction mix and cache miss rates. parameter symbol test conditions r4640 80mhz r4640 100mhz r4640 133mhz units min max min max min max pipeline clock frequency pclk 50 80 50 100 50 133 mhz masterclock high t mchigh transition t mchigh 6??ns masterclock low t mclow transition t mclow 6??ns masterclock frequency 25 40 25 50 25 67 mhz masterclock period t mcp 254020401540ns clock jitter for masterclock t jitterin (1) 250 250 250 ps masterclock rise time t mcrise (1) ???ns masterclock fall time t mcfall (1) ???ns modeclock period t modeckp (1) 256* t mcp 256* t mcp 256* t mcp ns
r4640/rv4640 commercial temperature range 16 system interface parameters?4640 boot-time interface parameters?4640 parameter symbol test conditions r4640 80mhz r4640 100mhz r4640 133mhz units min max min max min max data output t dm = min t do = max mode 14..13 = 10 (fastest) 1.0 (1) 11 1.0 (1) 9 1.0 (1) 9ns mode 14..13 = 01 (slowest) 2.0 (1) 15 2.0 (1) 12 2.0 (1) 12 ns data output hold t doh * mode 14..13 = 10 (fastest) 1.0 1.0 1.0 ns data setup t ds t rise = 5ns t fall = 5ns 6.5 5.5 4.5 ns data hold t dh 3 2 1.5 ns * 25pf loading on external output signals, fastest settings. parameter symbol test conditions r4640 80mhz r4640 100mhz r4640 133mhz units min max min max min max mode data setup t ds 3?? master clock cycle mode data hold t dh 0?? master clock cycle
r4640/rv4640 commercial/industrial temperature range 17 dc electrical characteristics ?commercial temperature range?4640 ( v cc = 5.0 5 %, t case = 0 c to +85 c) power consumption?4640 parameter r4640 80mhz r4640 100mhz r4640 133mhz conditions minimum maximum minimum maximum minimum maximum v ol 0.1v 0.1v 0.1v |i out |= 20ua v oh v cc - 0.1v v cc - 0.1v v cc - 0.1v v ol 0.4v 0.4v 0.4v |i out |= 4ma v oh 3.5v 2.4v 2.4v v il ?.5v 0.8v ?.5v 0.2v cc ?.5v 0.2v cc v ih 2.0v v cc + 0.5v 2.0v v cc + 0.5v 2.0v v cc + 0.5v i in 10ua 10ua 10ua 0 v in v cc c in (1) 15pf 15pf 15pf c out (1) 15pf 15pf 15pf i/o leak 20ua 20ua 20ua input/output leakage parameter r4640 80mhz r4640 100mhz r4640 133mhz conditions typical max typical max typical max system condition: 80/40mhz 100/50mhz 133/44mhz i cc standby 50 ma b 75 ma b 100 ma b c l = 0pf 125 ma b 150 ma b 200 ma b c l = 50pf active 575 ma b 800 ma b 700 ma b 1000 ma b 950 ma b 1350 ma b c l = 0pf no sysad activity 625 ma b 1000 ma b 750 ma b 1200 ma b 1000 ma b 1550 ma b c l = 50pf r4x00 compatible writes, t c = 25 o c 625 ma b 1100 ma a 750 ma b 1350 ma a 1000 ma b 1650 ma a c l = 50pf pipelined writes or write re-issue, t c = 25 o c a. these are the speci?ations idt tests to insure compliance. b. these are not tested. they are the result of engineering analysis and are provided for reference only.
r4640/rv4640 commercial temperature range 18 ac electrical characteristics ?commercial/industrial temperature range?v4640 (v cc =3.3v 5%; t case = 0 c to +85 c) clock parameters?v4640 (2) parameter symbol test conditions rv4640 80mhz rv4640 100mhz rv4640 133mhz rv4640 150mhz units min max min max min max min max pipeline clock frequency pclk 50 80 50 100 50 133 50 150 mhz masterclock high t mchigh transition t mcrise/fall 6? 3? ns masterclock low t mclow transition t mcrise/fall 6? 3? ns masterclock frequency 20 40 25 50 25 67 25 67 mhz masterclock period t mcp 25402040 154015 40ns clock jitter for masterclock t jitterin (1) 250 250 250 250 ps masterclock rise time t mcrise (1) 55 44ns masterclock fall time t mcfall (1) 55 44ns modeclock period t modeckp (1) 256* t mcp 256* t mcp 256* t mcp 256* t mcp ns note that operation of the rv4640 is guaranteed only with the phase lock loop enabled.
r4640/rv4640 commercial/industrial temperature range 19 system interface parameters?v4640 boot-time interface parameters?v4640 parameter symbol test conditions rv4640 80mhz rv4640 100mhz rv4640 133mhz rv4640 150mhz units min max min max min max min max data output t dm = min t do = max mode 14..13 = 10 (fastest) 1.0 (1) 11 1.0 (1) 9 1.0 (1) 9 1.0 (1) 9ns mode 14..13 = 01 (slowest) 2.0 (1) 15 2.0 (1) 12 2.0 (1) 12 2.0 (1) 12 ns data output hold t doh* mode 14..13 = 10 (fastest) 1.0 1.0 1.0 1.0 ns data setup t ds t rise = 3ns t fall = 3ns 6.5 5.5 4.5 4.5 ns data hold t dh 3 2 1.5 1.5 ns note: * 25pf loading on external output signals, fastest settings parameter symbol test conditions rv4640 80mhz rv4640 100mhz rv4640 133mhz rv4640 150mhz units min max min max min max min max mode data setup t ds 3??? master clock cycle mode data hold t dh 0??? master clock cycle
r4640/rv4640 commercial temperature range 20 dc electrical characteristics ?commercial/industrial temperature range?v4640 ( v cc = 3.3 5 %, t case = 0 c to +85 c) power consumption?v4640 parameter rv4640 80mhz rv4640 100mhz rv4640 133mhz rv4640 150mhz conditions min max min max min max min max v ol 0.1v 0.1v 0.1v 0.1v |i out |= 20ua v oh v cc - 0.1v v cc - 0.1v v cc - 0.1v v cc - 0.1v v ol 0.4v 0.4v 0.4v 0.4v |i out |= 4ma v oh 2.4v 2.4v 2.4v 2.4v v il ?.5v 0.2v cc ?.5v 0.2v cc ?.5v 0.2v cc ?.5v 0.2v cc v ih 0.7v cc v cc + 0.5v 0.7v cc v cc + 0.5v 0.7v cc v cc + 0.5v 0.7v cc v cc + 0.5v i in 10ua 10ua 10ua 10ua 0 v in v cc c in 15pf 15pf 15pf 15pf c out 15pf 15pf 15pf 15pf i/o leak 20ua 20ua 20ua 20ua input/output leakage parameter rv4640 80mhz rv4640 100mhz rv4640 133mhz rv4640 150mhz conditions typical max typical max typical max typical max system condition: 80/40mhz 100/50mhz 133/44mhz 150/50mhz i cc standby 40 ma b 50 ma b 60 ma b 60 ma b c l = 0pf 90 ma b 100 ma b 110 ma b 110 ma b c l = 50pf active 300 ma b 350 ma b 350 ma b 375 ma b 400 ma b 450 ma b 450 ma b 500 ma b c l = 0pf no sysad activity 325 ma b 375 ma b 375 ma b 400 ma b 450 ma b 500 ma b 500 ma b 550 ma b c l = 50pf r4x00 compatible writes, t c = 25 o c 350 ma b 450 ma a 400 ma b 450 ma a 500 ma b 575 ma a 550 ma b 625 ma a c l = 50pf pipelined writes or write re-issue, t c = 25 o c a. these are the speci?ations idt tests to insure compliance. b. these are not tested. they are the result of engineering analysis and are provided for reference only.
r4640/rv4640 commercial/industrial temperature range 21 physical specifications ?128-pin mquad/ pqfp 128 ld mquad mkt dwg (.80 ld pitch, gullwing) n/a symbols a min max 3.17 3.43 .30 .45 a1 a2 d/e d1/e1 e .80 bsc tolerances unless otherwise specified frac dec angles %%p %%p %%p scale size drawing no. rev approvals date drawn checked sheet of do not scale drawing aa a integrated device technology, inc. 3001 stender way, santa clara, ca 95054 (408) 492-8333 fax (408) 727-2328 1 1 -- - 11/95 dt .25 .51 3.50 3.86 31.00 31.40 27.59 27.79 psc-4054 00 b j .20 ref h .89 ref l .68 - c .23 .13 r notes: 1. all dimensions are in millimeters. h x 45 0 pin 1 id j x 45 0 3x l 7 0 c a1 a2 a e d d1 e e1
r4640/rv4640 commercial temperature range 22 r4640-32 pqfp/mquad package pin-out n.c. pins should be left ?ating for maximum ?xibility as well as for compatibility with future designs. an asterisk (*) identifies a pin that is active when low. pin function pin function pin function pin function 1 n.c. 33 vcc 65 vcc 97 vcc 2 syscmd2 34 vss 66 sysad28 98 vss 3 vcc 35 sysad13 67 coldreset* 99 sysad19 4 vss 36 sysad14 68 sysad27 100 validin* 5 sysad5 37 vss 69 vss 101 vcc 6 wrrdy* 38 vcc 70 vcc 102 vss 7 modeclock 39 sysad15 71 n.c. 103 sysad18 8 sysad6 40 vss 72 sysad26 104 int0* 9 vcc 41 vcc 73 n.c. 105 sysad17 10 vss 42 sysadc1 74 vss 106 vcc 11 syscmd3 43 vss 75 vcc 107 vss 12 sysad7 44 vcc 76 sysad25 108 int1* 13 syscmd4 45 masterclock 77 vss 109 sysad16 14 vcc 46 vssp 78 vcc 110 int2* 15 vss 47 vccp 79 sysad24 111 vcc 16 sysadc0 48 vss 80 sysadc2 112 vss 17 syscmd5 49 vss 81 vss 113 int3* 18 sysad8 50 vss 82 vcc 114 sysad0 19 vcc 51 vss 83 nmi* 115 int4* 20 vss 52 vss 84 sysad23 116 vcc 21 syscmd6 53 vss 85 release* 117 vss 22 sysad9 54 sysadc3 86 vss 118 sysad1 23 vcc 55 vccok 87 vcc 119 int5* 24 vss 56 vss 88 sysad22 120 sysad2 25 syscmd7 57 vcc 89 modein 121 vcc 26 sysad10 58 sysad31 90 rdrdy* 122 vss 27 syscmd8 59 vss 91 sysad21 123 syscmd0 28 vcc 60 vcc 92 vss 124 sysad3 29 vss 61 sysad30 93 vcc 125 vcc 30 sysad11 62 sysad29 94 extrqst* 126 vss 31 syscmdp 63 reset* 95 sysad20 127 syscmd1 32 sysad12 64 vss 96 validout* 128 sysad4
r4640/rv4640 commercial/industrial temperature range 23 ordering information valid combinations idt79r4640 - 80, 100, 133mhz mquad package, commercial temperature idt79rv4640 - 80, 100, 133, 150mhz pqfp package, commercial temperature idt79rv4640 - 100,133mhz pqfp package, industrial temperature idt79 yy xxxx 999 a a operating voltage device type speed package temp range/ process r rv 4640 80 100 133 mu blank commercial (0 c to +85 c case) 128-pin mquad 80 mhz pclk 100 mhz pclk 133 mhz pclk orion processor for embedded systems 5.0+/-5% 3.3+/-5% du 128-pin pqfp 150 mhz pclk 150 i industrial (-40 c to +85 c case)

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